1. Field of the Invention
The present invention relates to a semiconductor memory testing apparatus for testing memories formed by semiconductor integrated circuits and, more particularly, to an improved semiconductor memory testing apparatus which is provided with a plurality of pattern generators and capable of testing high-speed semiconductor memories in addition to normal speed semiconductor memories.
2. Description of the Related Art
Writable/readable memories such as RAMs (random access memories) are mostly formed by semiconductor integrated circuits (ICS). Roughly speaking, conventional semiconductor memory testing apparatus for testing such memories formed by semiconductor ICS (which memories will hereinafter be referred to as semiconductor memories) comprises a timing generating part 14, a pattern generator 11, a waveform shaping part 12, a logical comparison part 13 and a failure analysis memory.
The timing generating part 14 supplies a reference clock, which functions as a timing signal, to the pattern generator 11, the waveform shaping part 12 and the logical comparison part 13 to control their operations. The pattern generator 11 responds to the reference clock (the operation or working clock) from the timing generating part 14 to generate address pattern data, test pattern data and so forth to be applied to a semiconductor memory under test DUT, and to generate expected pattern data and the like to be fed to the logical comparison part 13. The waveform shaping part 12 converts such pieces of pattern data (digital signals) from the pattern generator 11 to analog pattern signals having real waveforms for supply to the semiconductor memory under test DUT.
The semiconductor memory under test DUT is controlled by the application thereto of a control signal to write therein or read out thereof the test pattern signals. That is, by the application of a write control signal to the semiconductor memory DUT, the test pattern signals are sequentially written thereinto at addresses specified by address pattern signals, whereas by the application of a readout control signal to the semiconductor memory DUT, the written test pattern signals are sequentially read out of its addresses specified by the address pattern signals.
The response output signal thus read out of the semiconductor memory DUT (hereinafter referred to also as a memory under test DUT) is provided to the logical comparison part 13 for logical comparison with the expected pattern data (a digital signal) output from the pattern generator 11. When a mismatch is found between them, the logical comparison part 13 produces a fail signal indicating the mismatch, i.e. what is called failure data. Usually, the logical comparison part 13 outputs a high logical level "1" (H logic) as the failure data. On the other hand, when a match is found, the logical comparison part 13 yields pass signal indicting the match, i.e. pass data. Since the failure data is logic "1", the logical comparison part 13 outputs low logical level "0" (L logic) as the pass data. The failure data is sent to the failure analysis memory and stored therein. Further, the failure analysis memory is not a prime constituent of the present invention, and hence it is not shown.
The failure analysis memory has the same operation speed and the same storage capacity as does the memory under test and the same address pattern signal as that applied to the memory under test is fed to this failure analysis memory as well. Furthermore, the failure analysis memory is initialized prior to the start of the test. For example, in the case where logic "0" is written into the failure analysis memory at its all addresses by initialization and failure data is provided from the logical comparison part 13 in the test of the memory under test, logic "1" is written into the failure analysis memory at an address specified by the address pattern signal. In other words, failure data (logic "1") indicting a defective or failure memory cell is written into the failure analysis memory at the same address as that of the failure memory cell of the memory under test.
Upon completion of one test cycle, it is decided whether the memory under test is defective or non-defective, taking into account the number of pieces of failure data and their locations stored in the failure analysis memory. For example, in the case of relieving a defective memory, the number of pieces of failure data (positional information of defective or failing memory cells of the memory under test) read out of the failure analysis memory is counted and a decision is made as to whether the detected defective memory cells can be relived by relief means provided in the memory under test.
Conventionally, a semiconductor memory of an operating speed equal to or lower than that of the pattern generator 11 is tested using the semiconductor memory testing apparatus of such a construction as shown in FIG. 6, whereas a high-speed semiconductor memory operable at a speed higher than that of the pattern generator 11 is tested using a semiconductor memory testing apparatus such as depicted in FIG. 7.
As shown in FIG. 7, the semiconductor memory testing apparatus is equipped with plural pattern generators 11A and 11B, two in this example. Pattern data from the pattern generators 11A and 11B are multiplexed by a high-speed conversion part 16 into high-speed pattern data, which is converted by the waveform shaping part 12 into a high-speed pattern signal having a real waveform for application to the memory DUT.
The operation clock (a reference clock) from the timing generating part 14 is applied directly to the waveform shaping part 12 and the logical comparison part 13, but the operation clock is given to the pattern generators 11A and 11B after being frequency divided into 1/2 in a clock/select signal generating part 15. Consequently, the pattern generators 1A and 11B generate, in response to an operation clock having a frequency of 1/2 of that of the reference clock (hereinafter referred to as 1/2 operation clock), such pattern data PA (composed of data A1, A2, A3, . . . ) and pattern data PB (composed of data B1, B2, B3, . . . ) as shown in FIGS. 8C and 8D, respectively, which have a period twice longer than that of the reference clock (i.e., a frequency of 1/2 of that of the latter).
The pattern data PA and PB are supplied to AND gates G1 and G2 at one input terminals thereof, respectively, the AND gates G1 and G2 forming the high-speed conversion part 16. To the other input terminals of the AND gates G1 and G2 are applied from the clock/select signal generating part 15, respectively, select signals SA and SB having a period twice longer than that of the reference clock and their duty factor of one-half (50%) as shown in FIGS. 8A and 8B.
As is evident from FIGS. 8A and 8B, since the select signals SA and SB have the same periods as those of the pattern data PA and PB but each has a duty factor of one-half as mentioned above, the select signals SA and SA each have a pulse waveform in which a high logical level (logic "1") of a duration corresponding to the one-half period of the pattern data is followed by a low logical level (logic "0") of a duration corresponding to the one-half period of the pattern data, and they are shifted in their phase by one-half period. Hence, the AND gates G1 and G2 which are supplied with the select signals SA and SB at one input terminals thereof, respectively, are alternately enabled (ON) and disabled (OFF) at a speed twice higher than the pattern data PA and PB that are fed to the other input terminals of the AND gates.
In the example of FIG. 8, the select signal SB that is applied to the AND gate G2 is delayed by the one-half period relative to the select signal SA that is applied to the AND gate G1; hence, the AND gate G1 permits the passage therethrough of only the first half (1/2) of each data A1, A2, A3, . . . of the pattern data PA supplied thereto and the AND gate G2 permits the passage therethrough of only the latter half (1/2) of each data B1, B2, B3, . . . of the pattern data PB supplied thereto. In consequence, an OR gate outputs high-speed pattern data PAB which is an alternation of the first half of each data of the pattern data PA and the latter half of the pattern data PB and has a frequency twice higher than those of the pattern data PA and PB.
The high-speed pattern data PAB that is output from the high-speed conversion part 16 is converted by the waveform shaping part 12 to a high-speed pattern signal having a real waveform, which is applied to the memory DUT. When the data written in the memory pUT is read out therefrom, the high-speed pattern data PAB from the high-speed conversion part 16 is provided as expected pattern data to the logical comparison part 13 for logical comparison with the data read out of the memory DUT to make a decision about whether the memory DUT is defective or non-defective.
Incidentally, various electronic apparatuses including computers mostly employ, as a main memory, a dynamic random access memory commonly called a DRAM. As is well-known in the art, the DRAM has, due to its device construction, a property that stored contents of memory cells disappear unless they are accessed within a certain period of time, and means is needed to refresh the DRAM periodically. On this account, in the case of testing the DRAM, the memory testing apparatus refreshes it at fixed time intervals in addition to the pattern signal write and readout operations that are operations of the main routine. That is, a refresh routine for sequentially accessing memory cells of the DRAM is provided separately of the main routine for testing the function of the DRAM so that the operation branches from the main routine to the refresh one at. regular time intervals and, upon completion of the refresh routine, returns to the main routine.
FIG. 9A schematically shows an example of the main routine and FIG. 9B an example of the refresh routine in the case of testing the DRAM through the use of one pattern generator as shown in FIG. 6.
As depicted in FIG. 9A, when the main routine is started, "10" is set in a branch address storage register and a timer is started which measures the time when to branch to the refresh routine. Now, let it be assumed that the address of the DRAM under test increments one by one, starting at "0" and ending in the largest number. For example, if the DRAM has a total of "1023" addresses, the first address is "0" and the last address "1023". Thus, the address to be refreshed first is the address "0".
The first-half routine L1 surrounded by the chain line indicates the execution of an operation of writing logic "0" in all addresses of the DRAM. In first step SP1 immediately after the start of the main routine, the first main routine address of the DRAM is set at "0". That is, the main routine starts at the address "0".
Next, in second step SP2 the pattern generator is caused to generate pattern data for writing logic "0" in the first address "0"of the DRAM. After the generation of the pattern data, a 1 is added to the first main routine address to provide a state in which logic "0" can be written in the next address "1".
In third step SP3 a check is made to see if the main routine address "1" is the last address of the DRAM. If not, the operation returns to second step SP2, in which the pattern generator is caused to generate pattern data for writing logic "0" in the next main routine address "1" of the DRAM and a 1 is added to the main routine address "1".
Thereafter, second and third steps SP2 and SP3 loop until the main routine address reaches the last address of the DRAM under test. When the main routine address reaches the last address of the DRAM, the operation proceeds to the second-half routine L2 surrounded by the chain line.
The second-half routine L2 begins with step SP4 of reading out of the DRAM the logic "0" written at its first address "0" in the routine L1. Next, in fifth step SP5 the pattern generator is controlled to generate pattern data for writing logic "1" at the first address "0" from which the logic "0" was read out in fourth step SP4, then a 1 is added to the first address "0" from which the logic "0" was read out, and logic "0" is read out of the next main routine address "1" so that logic "1" can be written therein.
In the next sixth step SP6, a check is made to see if the main routine address is the last address of the DRAM under test. If not, then the operation goes back to fourth step SP4 of reading out of the DRAM the logic "0" written at the next main routine address "1", followed by fifth step SP5 wherein thd pattern generator is caused to generate pattern data for writing logic "1" in the main routine address "1" from which logic "0" was read out and then a 1 is added to this address "1".
Thereafter, fourth to sixth steps SP4 to SP6 loop until the main routine address reaches the last address of the DRAM under test. When the main routine address reaches the last address of the DRAM, the second-half routine L2 ends, with which the main routine finishes.
Thus, the second-half routine L2 is a repetition of the operation of reading out logic "0" from each address of the DRAM under test and writing therein logic "1" for each of the first address "0" to the last one ("1023", for instance).
When the timer (started at the start point of the main routine as referred to previously) measures the preset time during the execution of the main routine, an interrupt instruction is issued irrespective of which step of the main routine is being executed and the operation of the main routine shown in FIG. 9A is suspended and then switched to the refresh routine depicted in FIG. 9B.
The refresh routine begins with step SP7, wherein a first refresh address "0" of the DRAM under test, preset at the start of the main routine, is accessed (logic "0" is rewritten) and a 1 is added to the first refresh address "0", permitting access to the next refresh address "1".
Next, a check is made in step SP8 to see if the number of times the refresh operation has been performed reaches a preset value N, where N is the number of addresses that are refreshed at one time and it is usually set at an integral fraction of the sum total of addresses of the DRAM under test. In this example, since the number of addresses is set at 16, it is decided in step SP8 whether the refresh operation is sixteenth.
When steps SP7 and SP8 have looped N times, the operation returns to the main routine of FIG. 9A. At this time, the address refreshed last is stored in a storage part so that when the refresh routine is again branched from the main routine, the refresh operation can be resumed at an address next to that where the preceding refresh operation concluded.
FIG. 10 illustrates in block form the general circuit configuration of the pattern generator 11 with which it is possible to perform the above-described refresh operation. FIG. 11 shows an example of its operation. The pattern generator 11 comprises a sequence control part 100, a pattern generating instruction memory 101 and a pattern generation control part 102. Following a pattern generating instruction that is read out of the pattern generating instruction memory 102 in accordance with the address (a value PC) of the instruction to be executed that is indicated by a program counter 103 of the pattern generator 11, the pattern generation control part 102 outputs pattern data PTNDT (a digital signal) and expected pattern data EXPDT.
What is intended to mean by a "main routine address" in FIG. 11 is the address of an address signal that is output accompanying the pattern data which is generated by the pattern generation control part 102 in FIG. 10 during execution of the main routine of FIG. 9A. A refresh routine address is the address of an address signal that is output accompanying the pattern data PTNDT which is generated by the pattern generation control part 102 during execution of the refresh routine of FIG. 9B.
Steps SP1, SP2, SP4, SP5 and SP7 in FIG. 9 are performed when the value PC indicated by the program counter 103 takes the values PC=0, PC=1, PC=2, PC=3 and PC=10 indicated on the right of the blocks of these steps, respectively. The instructions that are executed by steps SP1, SP2, SP4, SP5 and SP7 are prestored in the pattern generating instruction memory 101 (FIG. 10).
A sequence control instruction memory 104 follows the value PC of the program counter 103 to output sequence control instructions that determine the sequence of pattern generation. These sequence control instructions are prestored in the sequence control instruction memory 104.
A branch address storage register 105 in FIG. 10 is one that stores the value PC to be indicated by the program counter 103 when the instruction of the first box (step SP7) of the refresh routine in FIG. 9B is executed. In the example of FIG. 9B the value PC=10 is stored in the register 105.
A timer 106 in FIG. 10 is a means for measuring the time from the start of the main routine to the branching therefrom of the refresh routine. The timer 106 counts clock pulses output from a timer oscillator 107 and applies an interrupt signal to a synchronization circuit 108 each time the count value reaches a preset value. The synchronization circuit 108 synchronizes the interrupt signal with the clock signal from the timing generating part 14 (FIGS. 6 and 7) and provides it as a branch instruction J to a decode/select part 109.
In the example of FIG. 9, the generation of the pattern data PTNDT is started with the value PC of the program counter 103 set at 0 (PC=0). Thereafter, the instruction that is read out of the sequence control instruction memory 104 following the value PC of the program counter 103 is interpreted in the decode/select part 109, which determines the value PC of the program counter 103 for the next pattern generation cycle, thereby controlling the sequence of pattern generation. The pattern generating instruction is read out of the pattern generating instruction memory 101 in accordance with the value PC of the program counter 103 and the pattern generation control part 102 follows the read-out pattern generating instruction to generate the pattern data PTNDT and the expected pattern data EXPDT.
Upon input thereinto the branch instruction J from the synchronization circuit 108, the decode/select part 109 sets the value PC of the program counter 103 for the next pattern generation cycle at the value prestored in the branch address storage register 105, PC=10 in this example, regardless of the instruction inputted to the decode/select part 109 from the sequence control instruction memory 104. At the same time, the value (step of the main routine) that the program counter 103 ought to indicate in the next pattern generation cycle when it follows an instruction from the sequence control instruction memory 104 is written into a return address storage register 110. In the example of FIG. 11, PC=3 (step SP5) is written in the return address storage register 110 since the branch instruction is issued when the value of the program counter 103 is PC=2 (step SP4).
When the program counter 103 outputs the value PC=10 prestored in the branch address storage register 105, the pattern generating operation of the main routine is suspended and the refresh routine of FIG. 9B is branched.
When the instruction that is provided to the decode/select part 109 from the sequence control instruction memory 104 indicates the completion of the refresh routine during execution of the refresh routine, the value PC of the program counter 103 for the next pattern generation cycle is set at a value stored in the return address storage register 110. Since in this example PC=3 (step SP5) is prestored in the return address storage register 110 as mentioned above, the value PC of the program counter 103 is set at "3" (PC=3). With this, the pattern generating operation returns from the refresh routine to the main routine of FIG. 9A.
The above operations will be further described with reference to FIG. 11. At the same time as the main routine starts, the timer 106 is started. In pattern generation cycle 1, it shows that the value of the program counter 103 is "0" (PC=0), the main routine address is indefinite and the refresh routine address is "0".
In pattern generation cycle 2, the value of the program counter 103 is PC=1 and, as the result of execution of step SP1 (PC=0) of the main routine, the main routine address is "0" (the initial address).
In pattern generation cycle 3, the value of the program counter 103 is PC=1 and, as the result of execution of step SP2 (PC=1) of the main routine, the main routine address is added with a 1 and hence is "2".
Thereafter, the above-described operation is repeated to write logic "0" in all the addresses from "0" through "63" until a pattern generation cycle 65 is initiated; that is, the routine L1 in FIG. 9A is executed.
In the illustrated example, since the main routine address of the memory DUT (DRAM) starts at "0" and ends in "63", the first address is "0" and the last address "63". As regards the pattern generation cycle, the pattern generation cycle 2 corresponds to the main routine address "0", and consequently, the pattern generation cycle 65 corresponds to the main routine address "63". Accordingly, the routine L2 starts with the next pattern generation cycle 66 and executes steps SP4 to SP6.
In the routine L2, steps SP4 and SP5 are repeatedly performed until the main routine address reaches the last address "63" as described above. Hence, the value PC of the program counter 103 alternates between 2 (PC=2) and 3 (PC=3).
The FIG. 11 example shows the case where the timer 106 issues an interrupt signal in the pattern generation cycle 70, and consequently in this pattern generation cycle the branch instruction J is provided from the synchronization circuit 108 to the decode/select part 109. Responding to the branch instruction, the decode/select part 109 sets, in the program counter 103, the value 10 in the branch address storage register 105 as a value that the program counter 103 is to take in the next pattern generation cycle. At the same time, the value that the program counter 103 is to output when the pattern generating operation returns from the refresh to the main routine, i.e. "3" in this example, is stored in the return address storage register 110.
Thus, as shown in FIG. 11, the program counter 103 outputs a value 10 (PC=10) in a pattern generation cycle 71 that is the first pattern generation cycle after the pattern generating operation proceeds to the refresh routine. Furthermore, as shown in FIG. 11, the program counter 103 outputs a value 3 (PC=3) in a pattern generation cycle 87 which is the first pattern generation cycle after the pattern generating operation returns to the main routine.
In the refresh routine, the value PC of the program counter 103 remains at PC=10 and the main routine address is fixed at "2" but the refresh routine address is incremented one by one. Since the number of addresses that are refreshed at one time is 16 in this example, the refresh routine ends when it is executed 16 times, and the operation returns to the main routine.
When the operation returns to the main routine, the value PC of the program counter 103 is set at 3 stored in the return address storage register 110 and in a pattern generation cycle 87 that is the first pattern generation cycle after the operation returns to the main routine, the program counter 103 outputs a value "3" (PC=3) as shown in FIG. 11. Thus, step SP5 is performed in the pattern generation cycle 87.
From the above it will be understood that the pattern generator 11 shown in FIG. 10 is capable of performing the main and refresh routines alternately and operates normally.
Further, in the case of generating high-speed pattern data through the use of plural such pattern generators as shown in FIG. 7, they cannot be operated correctly or normally for the reasons given below.
For example, in the case where two pattern generators 11A and 11B are disposed side by side as depicted in FIG. 7 so that they generate the pattern data PA (A1, A2, A3, . . . ) and PB (B1, B2, B3, . . . ) shown in FIGS. 8C and 8D which are combined to obtain a high-speed pattern data in the high-speed conversion part 16, synchronization circuits 108A and 108B of the pattern generators 11A and 11B issue branch instructions JA and JB in different pattern generation cycles, resulting in the pattern generators 11A and 11B proceeding from the main to the refresh routine at different timings.
FIG. 12 shows an example of the foregoing. Assume that each of the pattern generators 11A and 11B is one that, in response to the branch instruction issued during execution of the main routine of the pattern generating operation, proceeds therefrom to the refresh routine to refresh the DRAM under test and, upon completion of the refresh operation, returns to the main routine for the pattern generating operation as described previously with reference to FIG. 10. FIG. 12 shows the case where when the two pattern generators 11A and 11B are operated, the timer (106A) of the pattern generator 11A generates an interrupt signal in the pattern generation cycle 36, but the timer (106B) of the pattern generator 11B earlier generates an interrupt signal in the pattern generation cycle 34. That is, in the pattern generator 11A the branch instruction JA is issued from the synchronization circuit 108A during execution of the pattern generation cycle 36, whereas in the pattern generator 11B the branch instruction JB is issued from the synchronization circuit 108B during execution of the pattern generation cycle 34.
Even if the timers of the pattern generators 11A and 11B are exactly identical in construction, their measurements of time often differ due to unevenness of or variations in characteristics of the components or parts constituting each timer or the like. As a result, there occurs such a disadvantage as shown in FIG. 12.
As mentioned above, when the branch instructions JA and JB are issued at different timings or time points, the situation arises where although the pattern generator 11A is generating pattern data for the execution of the main routine, the other pattern generator 11B is already generating pattern data for the refresh routine, resulting in a drawback that the correlation is lost between the pattern data.